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Synthesis of a Test Generator for a Built-ln Self-Test Scheme
| dc.contributor.author | Khomich , O. V. | ru |
| dc.contributor.author | Yarmolik, V. N. | ru |
| dc.coverage.spatial | Brest | ru |
| dc.date.accessioned | 2021-07-27T08:09:31Z | |
| dc.date.available | 2021-07-27T08:09:31Z | |
| dc.date.issued | 1999 | |
| dc.identifier.citation | Khomich, O. V. Synthesis of a Test Generator for a Built-ln Self-Test Scheme / O. V. Khomich,V. N. Yarmolik // International Conference on Neural Networks and Artificial Intelligence ICNNAI'99 = Международная конференция по нейронным сетям и искусственному интеллекту ICNNAI'99 : Proceedings, Brest, Belarus, 12–15 October 1999 / Brest Polytechnic Institute, Department of Computers and Laboratory of Artificial Neural Networks, Belarus Special Interest Group of International Neural NetWork Society, International Neural NetWork Society, Belarusian State University of Informatics and Radioelectronics (Belarus), Belarusian Academy of Sciences, Institute of Engineering Cybemetics (Belarus), Universidad Politechnica de Valencia (Spain), Institute of Computer Information Technologies (Ukraine, Ternopil) ; ed. V. Golovko. – Brest : BPI, 1999. – P. 198–203. | ru |
| dc.identifier.uri | https://rep.bstu.by/handle/data/20661 | |
| dc.description.abstract | This paper presents a new algorithm for the automated synthesis of pseudo-random test patterns generators for Built-ln Self Test schemes with a mixed testmode. The experimental resulls showan opportunity of using the given method on a design stage of circuits producing In this paper it is shown that an appropriat selection of test pattern generator can significantly reduce the hardware requirements of deterministic part. | ru |
| dc.language.iso | en | ru |
| dc.publisher | BPI | ru |
| dc.title | Synthesis of a Test Generator for a Built-ln Self-Test Scheme | ru |
| dc.type | Научный доклад (Working Paper) | ru |
